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1991-09-07
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HARDWARE OVERVIEW OF THE UOSAT-5 EARTH IMAGING SYSTEM
FILES
TECH_INF.003
UOSAT5.GIF (Pacsat protocol satellites only)
DISCUSSION
The UoSAT-5 Earth imaging system is composed of three basic units;
the CCD camera, video digitizer/buffer, and the image processing
hardware. The camera was constructed using the CCD04-06 monochrome
television sensor, and associated chip set manufactured by the EEV
company. It outputs a 2/3 inch format 578 X 576 pixel frame
arranged as two interlaced fields of 578 X 288 pixels, which is
compatible with the CCIR 625 line television standard. Exposure
control circuitry within the camera system provides a means of
improving image quality and adding flexibility. [See camera
specifications in Table I.]
The analog video signal produced by the camera is digitized and
stored in buffer memory in the main module. The image processing
hardware has access to the image buffer memory to read stored image
data for processing before transferring it to the onboard computer
(OBC) for downlink.
Video image processing is carried out onboard the satellite by the
Transputer Image Processing Experiment (TIPE). The TIPE is
comprised of two T800 transputers which can operate either
individually or as a pair. One of the processors, T1, is equipped
with a large amount of memory and a number of non-standard features
to provide a flexible image processing environment. The other
processor T0 is minimally equipped and was designed for high
reliability. T0 may act as a co-processor for T1 implementing a
parallel processing scheme, or as a backup should T1 fail. [See
Transputer specifications in Table II.]
TABLE I
CCD Camera Specifications
* EEV CCD04-06 image sensor and chipset.
* 578(horiz) x 576(vert) imaging array (two interlaced fields).
* 4.8 mm wide angle lens (fixed focus, fixed aperture).
* 1900 km x 1250 km area of coverage in 800 km orbit.
* 3 km mean spatial resolution.
* 2 km mean sub-nadir spatial resolution.
* 5 km mean edge of scene spatial resolution.
* 605 nm - 615 nm spectral band (orange).
* Digitally controlled gain and electronic exposure.
* 8-bit half-flash digitization for low-power (under 80 mW)
TABLE II
Transputer Specifications
Transputer 1
* IMS T800 (20 MHz) Commercial Spec.
* 2 MBytes of CMOS Static Random Access Memory (SRAM)
* Hardware Error Detection and Correction (EDAC) protection of all
memory.
* 350 ns memory cycle including EDAC operations (using 70 ns RAMs).
* Variable clock speed for power conservation.
* Control of image capture and exposure parameters.
* Access to Image Memory to read captured image data.
* 2 high-speed INMOS links to Transputer 1.
* 2 UARTs to spacecraft DASH serial busses.
* Bootable from ROM, spacecraft OBC or uplink.
* Single event upset (SEU) logging of program memory.
* SEU logging of transputer's internal memory (not used for
programs).
Transputer 0
* IMS T800 (17.5 MHz) to MilSpec 883C
* 16 k bytes of Silicon-on-Sapphire (SOS) SRAM program memory.
* 400 ns memory cycle.
* Fixed clock speed for reliability.
* Control of image capture and exposure parameters.
* Access ot Image Memory to read captured image data.
* 2 high-speed INMOS links to Transputer 1.
* 1 UART to spacecraft DASH serial bus.
* Bootable from Transputer 1 or spacecraft OBC.
* Current monitoring and SEU tests for SOS RAM.
Above information provided by UoSAT Spacecraft Engineering Research
Unit/Surrey Satellite Technology Ltd.
For More Information Contact:
Marc Fouquet or J. M. Radbone
UoSAT Spacecraft Engineering Research Unit
University of Surrey
Guildford, Surrey GU2 5XH United Kingdom
Tel: (0483) 509315 Fax: (0483) 34139